The product development cycle is under constant pressure to decrease cycle time by moving more quickly from the design phase to properly functioning hardware. The integration of test equipment and electronic design automation and simulation tools typically provides an improvement in product development cycle times. Current models for semiconductor devices do not take into account all of the parasitic elements associated with the way the devices are physically drawn, positioned, and connected.
To address this issue there is a set of electronic design automation tools referred to as “parasitic extractors” that can measure and provide this information for simulation purposes. Current parasitic extractors accurately extract parasitic devices between interconnections but depend on device models for the design devices. The device models may contain accurate parasitic information for the device itself, but do not account for the interactions afforded by its surroundings since its environment is usually unique and therefore not known at the time that the models were developed.
These tools currently deal with this problem by lumping all device parasitic elements together and assigning them to the terminals of the device. This approach provides an approximation to the reality of the silicon layout and can turn out to be a bad approximation, especially as device operating frequencies increase. This is particularly true in devices that are physically large. These devices encounter a higher level of interaction with surrounding devices and interconnections wherein much of the interaction is typically located in the body of the device and not at its terminals, as the current tools assume.
Accordingly, what is needed in the art is an enhanced way to account for the parasitic elements associated with devices embedded in a network.